Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect

A model for delay evaluation and minimization in paths composed of logic gates and RC wires is presented. The method, Unified Logical Effort (ULE), provides closed-form conditions for timing optimization while overcoming the breakdown of standard logical effort (LE) rules in the presence of interconnect. The ULE delay model unifies the problems of gate sizing and repeater insertion: In cases of negligible interconnect, the ULE method converges to standard LE optimization yielding tapered gate sizes. In the case of long wires, the solution converges towards uniform optimal sizing of the gates as in repeater insertion methodologies. The technique is applied to various logic path examples, in order to investigate the influence of wire length, gate type, and technology. Techniques for combining the ULE method with existing heuristics for buffering and repeater insertion are also proposed.